Highly skilled Design Verification Engineer with 2.7+ years of experience, proficient in Verilog, System Verilog, and UVM for developing and verifying complex digital designs. Expertise includes testbench development, power-aware verification (UPF), and debugging, with a strong foundation in industry-standard protocols like AXI, AHB, SPI, and I2C. Adept at leveraging scripting (Python, Perl) and automation to enhance verification efficiency and contribute to cutting-edge technology development.
Design Engineer - I
Hyderabad, Telangana, India
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Summary
As Design Engineer I, Sandeep currently drives power-aware verification for AMD's next-generation complex SoCs, focusing on UPF-based methodologies and ensuring high-quality design integrity.
Highlights
Led comprehensive test planning, regression execution, and failure debugging for complex SoCs, ensuring timely resolution of critical callouts.
Developed automation scripts in Python, Perl, and shell, streamlining regression processes, log analysis, and reporting, significantly boosting team productivity.
Contributed to the development and maintenance of robust verification environments for power domains and low-power features, enhancing system stability and performance.
Resolved complex test failures, power domain-related mismatches, and simulation analogies through advanced debugging techniques, minimizing design flaws.
Mentored junior engineers on verification methodologies and scripting best practices, fostering team growth and accelerating onboarding.
Collaborated cross-functionally with RTL, DFT, DFD, and DV teams to align project goals, timelines, and verification strategies, ensuring seamless integration.
Engineer Trainee
Tirupati, Andhra Pradesh, India
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Summary
As an Engineer Trainee, Sandeep completed a 6-month intensive training program at VEDA IIT, gaining hands-on experience in industry-standard design verification tools and methodologies.
Highlights
Developed and verified robust testbenches for complex digital designs using Verilog, System Verilog, and UVM, ensuring functional correctness.
Automated verification processes and enhanced testbench development by leveraging Python and Perl scripting.
Collaborated with peers to debug and validate designs, significantly improving verification coverage and design reliability.
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B.Tech
Electronics and Communication Engineering
Grade: 8.2 CGPA
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Board of Intermediate
Intermediate
Grade: 975 Marks
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SSC
Secondary School Certificate
Grade: 10 Marks
Awarded By
Graduate Aptitude Test in Engineering (GATE)
Qualified in GATE ECE twice (2021, 2022) through self-preparation, achieving AIR 965 (IN) and 2635 (ECE).
Awarded By
Government of Andhra Pradesh
Awarded a meritorious scholarship covering full tuition fee reimbursement for undergraduate studies.
Issued By
Industry Certification
Issued By
Cadence Online
Verilog HDL, System Verilog, UVM, ASIC.
Synopsys VCS, Verdi.
C, C++, UPF, Python, Perl.
AHB, AXI, UART, I2C, SPI.
Perforce, Jenkins.
Linux, Windows.
Hospitality Panel, IEEE Student Chapter, Sports Club Treasurer.
Cricket Tournaments.
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Summary
Developed a comprehensive AMBA AXI4 Verification IP (VIP) from scratch using System Verilog and UVM, including all core UVM components.
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Summary
Developed and implemented a robust verification environment for a 16-bit synchronous circular FIFO.
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Summary
Developed a comprehensive controller for a newspaper vending machine.
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Summary
Designed and simulated an innovative fractal antenna for satellite communication, leveraging unique geometric properties to optimize performance across two different frequencies.