# Sandeep Kumar Marripudi - Design Verification Engineer
Source: https://hello.cv/sandeepmarripudi
ongole

## About
Highly skilled Design Verification Engineer with 2.7+ years of experience, proficient in Verilog, System Verilog, and UVM for developing and verifying complex digital designs. Expertise includes testbench development, power-aware verification (UPF), and debugging, with a strong foundation in industry-standard protocols like AXI, AHB, SPI, and I2C. Adept at leveraging scripting (Python, Perl) and automation to enhance verification efficiency and contribute to cutting-edge technology development.

## Work
### Design Engineer - I | SoCtronics (Onsite – AMD)
As Design Engineer I, Sandeep currently drives power-aware verification for AMD's next-generation complex SoCs, focusing on UPF-based methodologies and ensuring high-quality design integrity.
- Led comprehensive test planning, regression execution, and failure debugging for complex SoCs, ensuring timely resolution of critical callouts.
- Developed automation scripts in Python, Perl, and shell, streamlining regression processes, log analysis, and reporting, significantly boosting team productivity.
- Contributed to the development and maintenance of robust verification environments for power domains and low-power features, enhancing system stability and performance.
- Resolved complex test failures, power domain-related mismatches, and simulation analogies through advanced debugging techniques, minimizing design flaws.
- Mentored junior engineers on verification methodologies and scripting best practices, fostering team growth and accelerating onboarding.
- Collaborated cross-functionally with RTL, DFT, DFD, and DV teams to align project goals, timelines, and verification strategies, ensuring seamless integration.
### Engineer Trainee | Design Verification (VEDA IIT)
As an Engineer Trainee, Sandeep completed a 6-month intensive training program at VEDA IIT, gaining hands-on experience in industry-standard design verification tools and methodologies.
- Developed and verified robust testbenches for complex digital designs using Verilog, System Verilog, and UVM, ensuring functional correctness.
- Automated verification processes and enhanced testbench development by leveraging Python and Perl scripting.
- Collaborated with peers to debug and validate designs, significantly improving verification coverage and design reliability.

## Education
### Sree Vidyanikethan Engineering College | Electronics and Communication Engineering
8.2 CGPA
### Sri Chaitanya Junior College | Intermediate
975 Marks
### Sri Chaitanya High School | Secondary School Certificate
10 Marks

## Awards
### GATE ECE Qualification
Graduate Aptitude Test in Engineering (GATE) | 2022-01-01
Qualified in GATE ECE twice (2021, 2022) through self-preparation, achieving AIR 965 (IN) and 2635 (ECE).
### Meritorious Scholarship
Government of Andhra Pradesh | 2018-09-01
Awarded a meritorious scholarship covering full tuition fee reimbursement for undergraduate studies.

## Languages
- English
- Telugu

## Certificates
### Low-Power Simulations with IEEE Std 1801 UPF v22.09
Industry Certification | 2023-01-01
### System Verilog and Universal Verification Methodology
Cadence Online | 2023-01-01

## Skills
### HDL & Programming
- Verilog HDL
- System Verilog
- UVM
- ASIC
### Tools
- Synopsys VCS
- Verdi
### Programming & Scripting Languages
- C
- C++
- UPF
- Python
- Perl
### Protocols
- AHB
- AXI
- UART
- I2C
- SPI
### Version Control
- Perforce
- Jenkins
### Operating Systems
- Linux
- Windows

## Interests
### Community Engagement
- Hospitality Panel
- IEEE Student Chapter
- Sports Club Treasurer
### Sports
- Cricket Tournaments

## Projects
### Designed and implemented a comprehensive AMBA AXI4 Verification IP (VIP) from scratch using System Verilog and UVM.
Developed a comprehensive AMBA AXI4 Verification IP (VIP) from scratch using System Verilog and UVM, including all core UVM components.
### Verification of 16-bit synchronous circular FIFO
Developed and implemented a robust verification environment for a 16-bit synchronous circular FIFO.
### Controller - Newspaper Vending Machine
Developed a comprehensive controller for a newspaper vending machine.
### Design and Simulation of Fractal Antenna for satellite applications
Designed and simulated an innovative fractal antenna for satellite communication, leveraging unique geometric properties to optimize performance across two different frequencies.

## Source
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